Said Hamdioui

Research

I have been working on two main research lines: Emerging Computing paradigms based on emerging device technologies and Hardware Dependability.

Emerging Computing paradigms

The research on emerging computing paradigms targets the invention, design, prototyping and demonstration of disruptive computing accelerators/engines by making use of unique features of emerging devices such as memristors and spintronics, while mainly focusing on energy-constrained low-granularity computing for a wide range of edge applications, including AI, such as personalized healthcare, smart environments and drones.  Examples of topics include computation-in-memory, new hardware architectures of AI, neuromorphic computing, spin-wave computing, etc. we adapts a holistic approach in which it addresses the whole computing engine design stack. The research is being performed in many partners such as TU Eindhoven in the Netherlands, RWTH in Germany, IMEC in the Netherlands and Belgium, European Space Agency in the Netherlands, IBM in Switzerland and in USA, etc.

• Micro-architecture and circuit design: in which dedicated accelerators are defined and designed; logic and arithmetic operations are developed and designed based on emerging devices.
• Architecture design: where different specialized accelerator are integrated while considering different metrics such as optimization of communication, power and control logic, as well as maximizing the parallelism and throughput.
• Compilers and mapping methods: in which a programming interface and the mapping of (parallel) algorithms on the developed architecture are under study.
• Algorithms and application: in which applications and algorithms supporting massive parallelism are investigated in order to analyze their suitability for emerging computing paradigms/ architectures.

Hardware Dependability

Research on hardware dependability aims at developing appropriate solutions that can guarantee the manufactured chips/ hardware are reliable and trustworthy.  This research is being performed in collaboration with many partners such as NXP in the Netherlands, IMEC in Belgium, Cadence in USA, Qualcomm in USA, European Space Agency in the Netherlands, Polito Di Torino in Italy, Karlsruhe Institute of Technology in Germany, Rescure in The Netherlands, Netherlands Forensic Institute (NFI) in the Netherlands, etc. The focus of this research is:

• Testability: This includes understanding the weaknesses of new technology nodes and integration, developing appropriate fault models and test solutions that can enhance the outgoing product quality and reduce the cost. A lot of attention in our research is given to memories both traditional as well as emerging ones.
• Reliability: This includes the analysis of reliability failure mechanisms and their impact on the chip life time and failure rate, developing prediction models, design-for-reliability and mitigation schemes, etc.
• Hardware Security: This includes Physical Unclonable Functions technology for strong security and authentication solutions, analysis of security weaknesses of hardware and development of design-forsecurity solutions and secure ICs, etc.

Projects

List of some selected/ ongoing projects:

TIRAMISU “Training and Innovation in Reliable and Efficient Chip Design for Edge AI” (European HORIZON MSCA Doctoral Network project: Sept 2024- Aug 2028)

• Purpose: The general research objective of TIRAMISU is a practical methodology for reliable and energy-efficient Edge AI hardware backbone design and innovation management. The action will provide strong interdisciplinary training for future European engineers and researchers driving the innovation for reliable and energy-efficient Edge AI chips. 
• Collaborators: Tallinn University of Technology (Estonia), Politecnico di Torino (Italy), University of Cyprus (Cyprus), Cadence Design Systems (Germany), Infineon Technologies (Germany), IMEC (Netherlands), Dumarey Softronix (Italy), Fraunhofer-Gesellschaft (Germany), Bern University of Applied Science (Switzerland)

NL-ECO (Netherlands Initiative for Energy-Efficient Computing- Dutch National Science Agenda (NWA) program).

• Purpose: NL-ECO NL aims to develop new materials, technologies and scientific insights for energy-efficient information technology.  In an interdisciplinary approach, the NL-ECO program explores frontiers in energy-efficient computing technologies which go beyond existing paradigms. The focus is on the development and application of new chip technologies that combine electrical, optical and magnetic effects, on new ways of data processing inspired by the functioning of the brain, and on materials structured in such a way that they can perform calculations automatically.
• Collaborators: University of Twente, University of Groningen, TU Eindhoven, Radboud Univeristy Nijmgen, Fontys, IMEC, ASTRON, AMOLF, TNO, SAXION, ASML, Smart Photonics, SURF, ESA, Thales, IBM, etc.

• Ferro4Edge: (EU project, Horizon Europe, CL4-2023-Digital-Emerging-01-11: Jan 1, 2024- Dec 31, 2027)
• Purpose: Ferro4Edge (Scalable, ferroelectric based accelerators for energy efficient edge AI) aims at developing, designing and demonstrating ultra-low power, scalable edge accelerator for artificial intelligence incorporating a memory augmented neural network, based on low cost, high density, multi-level, Back End of Line (BEoL) integrated ferroelectric (FE) technology.
• Collaborators:  CEA (FR), NamLab (DE), Ecole Centrale de Lyon (FR), STMIcroelectronics (FR), SYNSENSE AG (CH), Ferroelectric Memory Company (DE).
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• NeuroKIT2: (EU project, European Union’s Horizon Europe research and innovation programme, Jun 2023- May 2026)
• Purpose:  The NEUROKIT2E project aims at proposing a Deep Learning Platform for Embedded Hardware around an established European value chain (providing AI hardware and software). This open source platform will provide the necessary tools for Europe to play on the same level with its American and Chinese competitors, and take the lead on a competitive aspect (still underdeveloped but which will quickly prove to be essential): embedded AI.
• Consorium: see link NeuroKIT2

• CONVOLVE (EU project, Horizon Europe, CL4-2021-Digital-Emerging-01: Sept 2022- Aug 2025)  
  • Purpose: CONVOLVE (Seamless design of Smart Edge Processors), empowered by a top EU consortium, aims at bringing EU in the lead for edge processor design, by improving energy-efficiency by 100x, a 10x faster design time, moving AI to the edge, while guaranteeing real-time safety and security.
  • Collaborators: TU Eindhiven (NL), KU Leuevn (BE/NL), Bosh (DE), NXP (DE), ETH Zurich (CH), Uni of Manchester (UK), Uni of Murcia (ES), Thales Alenia Sapce (ES),  ...

• DAIS (EU project, ECSEL, May 2021- April 2024)  
  • Purpose: The DAIS project researches and delivers distributed artificial intelligent systems. Our role in the project is to develop, design and demonstrate new hardware architectures based on emerging devices for edge AI; the focus is energy efficiency and reliability. Concepts such as computation-in-memory using memristor devices, spiking neural networks, low power design, etc will be investigated
  • Collaborators: IMEC (BE/NL), NXP (NL), ...
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• CHIRON (EU project/ FETOPEN, May 2018- April 2022)
  • Purpose: CHIRON targets a ground-breaking proof of principle of the essential elements for hybrid spin wave–CMOS computing. CHIRON will fabricate basic logic gates, such as inverters and majority gates, demonstrate their operation, and assess their performance. CHIRON will also develop magnetoelectric and multiferroic nanoresonators, based on nanoscale bulk acoustic resonators, which bear promise for high energy efficiency and large output signal. 
  • Collaborators: IMEC (BE), CNRS (FR), FORTH (GR), Thales (FR), UNIKL (DE), UPSud (FR), Solmates (NL), IMT (RO).
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• MNEMOSENE (EU project/ ICT: 2017-2021)
  • Purpose: Purpose: The project aims at demonstrating a new computation-in-memory (CIM) architecture based on resistive devices together with its required programming flow and interface. The targets are: (a) Design of new (Non-Von Neumann) CIM architecture based on a memristive device technology, (b) Design and test of memristor based logic and memories, (c) design of efficient on-chip communication schemes for computation in memory architecture, (d) Development and design of new mapping method and framework for efficient compilation and mapping of parallel algorithms on CIM architecture. 
  • Collaborators: Eindhoven University of Technology, IMEC, ARM, IBM, RWTH-Aachen, ETHZ, INRIA.

• RESCUE (EU project/ MSCA-ITN 2017-2021)
  • Purpose: Enhance design of complex systems at the next generation nanoelectronics technologies by addressing the demanding and mutually dependent aspects of reliability, security and quality, as well as corresponding electronic design automation tools.
  • Collaborators: Intrinsic Tallinn University of Technology, EE; BTU Cottbus-Senftenberg, DE; Politecnico di Torino, IT; Cadence Design Systems GmbH, DE; IROC Technologies, FR; Intrinsic-ID B.V., NL; IHP GmbH, DE. 

• TRACE (EU Project/ CATRENE 2016-2019)
  • Purpose: The project aims at developing a method including processes and tools required for the upgrade and qualified transfer of standard consumer electronic (CE) semiconductor components and technologies to the automotive domain. The method will be generally applicable to identify required modifications and adaptations as well as final conditions for qualification of CE components, technologies and resultant integrated systems for functionally safe and reliable automotive applications.
  • Collaborators/ Partners: NXP(NL), Heliox (NL), Catena (NL), UNi of Siegen (DE), Bosch (DE), BMW (DE), Volkswagen (DE), ST (FR), etc.

• REMAP (National peroject with ESA- 2016)
  • Purpose: The project aims at understating, characterizing and modelling different emerging reliability failure mechanisms, which are rising and becoming dominant with new generations of advanced DRAM technology nodes used in aerospace. In particular, the objectie are: a) Intensive characterization of different reliability failure mechanisms (including the emerging ones) on the reliability aspects; i.e., failure rates and life time for DRAM memories, b) Exploring the impact of other aspects such as technology scaling, temperature, process variations, Vdd variations, workload/application, etc., c) Development of accurate failure rate prediction models, d) Validation of the models using both simulation and experiments (measurements). 
  • Collaborators: Euorpean Space Agencey (NL).

• TUTORIAL (EU project/ H2020-TWINN- 2015)
  • Purpose: boost the scientific excellence and innovation capacity in the trans-disciplinary field of nanoelectronics based dependable cyber-physical systems (NBDCPS) of Tallinn University of Technology (TUT) and its high-quality Twinning partners. 
  • Collaborators/partners: Tallinn University of Technology (TUT), Politecnico di Torino (POLITO) and Deutsches Zentrum für Luft- und Raumfahrt (DLR).

Students

PostDocs

• Theofilos Spyrou 

Ongoing PhD Students

• Emerging Computing paradigms/ brain-inspired computing PhD Students
  • Ismail Bourhaeil (Sept 1, 2024): In-memory address calcualtion for energy effecient embedded applications, in collaboration with IMEC.
  • Konstantinos Stavrakakis (Jun 1, 2024): Simulation models for emerging memristor based edge AI accelrators (Ferro4Edge Project/ NEUROKIT project/ Convolve Project) 
  • Lennart Paul Liong Landsmeer, Memristor based Cerebellum-circuitry emulation, in collaboration with EMC (Erasmus Medical Centre, Rotterdam, The Netherlands). 
  • Zacharia Rudge, Memristor based AI accelerators for aerospace applications, in collaboration with European Space Agency (ESA).
  • Yash Biyani, FeFET based edge AI accelerators (Ferro4Edge Project). 
  • Asmae El Arrassi, SRAM based edge AI accelerators (Convolve Project).
• Test and Relaibility PhD students
  • Lohit Gandham (Oct 1, 2024): Self-Healing RRAM based Neuromorphic computing for edge AI (SNS project)
  • Sicong Yuan, Test and DfX for STT-MRAMs, in collaboration with IMEC. 
  • Hanzhi Xun, Test and DfX for RRAMs. 
  • Elena Soli, Cryo-CMOS reliability and testing.
• Hardware Security PhD Students 
  • Shayesteh Masoumian, Reliability analysis of SRAM-based PUFs in nano era.

Graduduated PhD students

1. Sumit Diware, Computation-in-Memory based Edge-AI for Healthcare: A cross-layer approach, October 29, 2024.
2. Abhairaj Singh, Logic and Arithmetic Computation-in-Memory Accelerators based on Memristor Devices, May 28, 2024.
3. Taha Shahroodi, Computation-in-Memory for Modern Applications using Emerging Technologies, March 12, 2024
4. Abdullah Aljuffri, Securing Power Side Channels by Design, Feb 27, 2024.
5. Mahdi Zahedi, Computation-in-memory: from application-specific to programmable designs,  Dec 22, 2023.
6. Felipe Augusto da Silva , EDA tools and methodologies for reliable nanoelectronic systems, Sept 21, 2022.
7. Moritz Fieback, Testing RRAMs and Computation-in-Memory Decvices, July 8, 2022. 
8. Abdulqader Nael Nathmi Mahmoud, Spin Wave Based Circuit Design, June 14, 2022. 
9. Guilherme Cardoso Medeiros, Test and Diagnosis of Hard-to-detect faults in FinFET SRAMs, June 10, 2022
10. Lizhou Wu, Testing STT-MRAM: manufacturing defects, fault Modes and test solutions; Graduted with Cum Laude, Feb 22, 2021. Winner McCluskey Best Doctoral Thesis Award at International Test Conference, Oct 2021. 
11. Jintao Yu, Computation-in-Memory: From Circuits to Compilers; Feb 5th, 2021. 
12. Daniel Kraak, Memory Reliability Analysis Framework: Modeling and Mitigation; Dec 14, 2020.
13. Prashant D. Joshi, Dependable Network Technologies, Oct 7, 2019.
14. Haoang Anh Du Nguyen, Computation-in-Mmeory based on Memristive devices, Sept 13, 2019
15. Innocent Agbo, Reliability Modeling and Mitigation for Embedded Memories, June 2018. Winner EDAA Outstanding Disseration Award at "Design Automation and Test in Eurrope", March 2019. 
16. Lei Xie, Memristive devices for logic design and computing, Feb 2018. 
17. Mafalda Cortez, Reliability Assessment and Test Methods for Anti-counterfeiting Technology, November 2015.
18. Motta Taouil, Yield and Cost Analysis for 3D Stacked ICs, Septmeber 2014. Graduated with Cum Laude. 
19. Seyab Khan, Bias Temperature Instability Analysis, Monitoring and Mitigation for Nano-Scaled Circuits, September 2013. 
20. Zaidi Haron, Testability and Fault Tolerance for Emerging Nanoelectronic Memories, May 2012.

 Ongoing Master Students

  Graduated  Master Students

1. Shubhendu Shrivastava, Stress Aware Quiescent Current Test Optimization, in collaboration with NXP,  Aug 24, 2021
2. Mudit Saxena,  Pre-Silicon Power Leakage Assessment Framework using Generative Adversarial Networks, Aug 23, 2021
3. Ryan van Leenen, Hardware-Based Methods for Memory Acquisition: Analysis and Improvements, Aug 23, 2021
4. Artemis Zografou, RRAM-based fault-tolerant Binary Neural Networks, July 27, 2021
5. Sudeshna Dash, Accurate & Energy efficient ECG Classification using RRAM based DNN Architecture, July 19, 2021.
6. L.J. Hamburger, BTI in SRAM: Mitigation for BTI ageing in SRAMs, Nov 25, 2020.
7. Hans Okkerman, Embedded Memory Security: Securing the IoT from the hardware level, Nov 30, 2020.
8. Pavan Talluri, Fault Classification and Vulnerability Analysis of Microprocessors, in collaboration with RISCURE (the Netherlands), Nov 4th, 2020
9. Remon F. J. van Duijnen, ISA and Hardware Design for a Pipelined Computation-in-Memory tile, June 1st, 2020.
10. Tijs Hol, Physical Defect Modling for RRAM, Aug 28, 2020.
11. Marc Zwalua, Thermal Side Channel Analysis, Oct 28, 2020.
12. Nourdin Ait El Mehdi, Analyzing the Resilience of Modern Smartphones Against Fault Injection Attacks, collaboration with RISCURE (the Netherlands), June 14, 2019.
13. M.L.J. van Beusekom, Circumventing Secure JTAG: A detailed plan of Attack, in collaboration with Netherlands Forensic Institute, June 13, 2019.
14. Abhairaj Singh, Circuit Design for Memristor Based In-Memory Computing, May 23, 2019
15. Pradeep Venkatachalam, S-Net: A Neural Network Based Countermeasures for AES, Aug 30, 2019.
16. Surya Nagarjan, Testing Computation-in-Memory Architectures Based on Emerging Memories, Nov 28, 2019.
17. Santosh S. Malagi, Library Characterization for Cell-Aware Test, in collaboration with IMEC (Belgium), Sept 18, 2018.
18. Michael Mainemer Lang, Quality and Cost modeling for 3D Stacked ICs, in collaboration with IMEC (Belgium) April 2018.
19. Abdullah Aljuffri, Exploring Deep Learning for Hardware Attacks, in collaboration with RISCURE (the Netherlands), April 2018.
20. Moritz Fieback, DRAM Reliability: Aging Analysis and Reliability Prediction Model, in collaboration with European Space Agency (ESA, the Netherlands), Dec 2017.  
21. Haji Akhundov, Development and Design of Lightweight public-key crypto core, in collaboration with Intrinsic ID (the Netherlands), Jan 2017.  
22. Daniel Kraak, Experimental and Industrial Evaluation of Variability Resilient Schemes, in collaboration with NXP Eindhoven (the Netherlands). December 2015.
23. Anteneh Gebregiorgis, Aging Mitigation Schemes for Embedded Memories, In collaboration with Karlsruhe Institute of Technology (KIT, Germany). July 2014
24. Gijs Roelofs 'Design for Testability for Secure ICs', Master Thesis, CE-MS-2012-10, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven, the Netherlands, October 2013.
25. Mahmoud Masadeh ’Interconnect Test for 3D Stacked Memories’, Master Thesis, CE-MS-2013-06, Delft University of Technology, the Netherlands, August 2013.
26. Abiram Pattabiraman, Experimental Wind Flow Studies For Development and Calibration Of Thermal Models For Photovoltaic Cells, Delft University of Technology, in collaboration with IMEC (Belgium), July 2013.
27. Christos Papameletis, 'Design-for-Testability Automation for 3D Stacked ICs', Master Thesis, CE-MS-2012-09, Delft University of Technology, in collaboration with IMEC (Belgium) and Cadence (USA), Augustus 2012.
28. Subin Sivadas, 'Sensorless Algorithm development for Field Oriented Motor Control', Master Thesis, CE-MS-2011-04, Delft University of Technology, in collaboration with NXP Nijmegen (the Netherlands), November 2011.
29. Vahid Roostaie, Design and analysts of a coherent memory subsystem for FPGA-based embeddedsystems, Master Thesis, CE-MS-2011-16, Delft University of Technology, in collaboration with Vec-torFabrics B.V. Eindhoven, The Netherlands, September 2011.
30. Apurva Dargar, 'Modeling SRAM start-up characteristics for Physical Unclonable Functions', Maste Thesis, CE-MS-2011-11, Delft University of Technology, in collaboration with Intrinsic ID Eindhoven,the Netherlands, July 2011. Graduated with Cum Laude.
31. Venkataraman Krishnaswami, 'A New Test Paradigm for Semiconductor Memories in the Nano-Era', Master Thesis, CE-MS-2011-14, Delft University of Technology, July 2011.
32. Vishwas Raj Jain, 'A Hierarchical Memory Diagnosis Approach: dealing with defects in all parts of the memory system', Master Thesis, CE-MS-2011-15, Delft University of Technology, July 2011. Graduated with Cum Laude.
33. Nivesh Rai, 'Defect Oriented Testing for Analog/Mixed-Signal Devices', Master Thesis, CE-MS-2011-10, Delft University of Technology, in collaboration with NXP Semiconductors, Eindhoven, July 2011.
34. Imran Achraf, 'MePoEfAr: Memory and Power Efficient Architecture for EmbeddedMicrocontrollers', Master Thesis, CE-MS-2011-17, Delft University of Technology, July 2011.
35. Halil Kukner, 'Generic and Orthogonal March Element based Memory BIST Engine' Master Thesis, CE-MS-2010-25, Delft University of Technology, September 2010.
36. Jouke Verbree, 'On 3D Stacked IC Yield Improvement and 3D-DfT Test Architecture', Master Thesis, CE-MS-2010-xx, Delft University of Technology, in collaboration with IMEC, Belgium, July 2010.
37. Zaiyan Ahyadi, 'Experimental Analysis on ECC Schemes for Fault Tolerant Hybrid Memories', Master Thesis, CE-MS-2009-xx, Delft University of Technology, November 2009.
38. Ghazaleh Nazarian, 'On-Line Testing for Routers in Networks on Chip', Master Thesis, CE-MS-2008-xx, Delft university of Technology, December 2008.
39. Fomin Nkengafeh Anne, 'Experimental Analysis of Design-For-Testability Techniques in SRAMs', Master Thesis, CE-MS-2008-xx, Delft university of Technology, October 2008.
40. Li Chuanyou, 'Testing Deep-submicron Embedded Memories in FPGAs', Master Thesis, CE-MS-2008-xx, Delft University of Technology in collaboration with Altera, San Jose, CA, USA, August 2008.

Honors/Awards

Honors, Awards, Nominations and Appointments  (selected)

MSc thesis/ PhD positions

PhD positions

At the moment we have around 8 open PhD/ PostDoc positions being parts of different European and National projects; topics are related to the following

• Microarchitecture design and implementation for FeFET based computation-in-memory accelerators for edge AI; building accelerator simulators for FeFET based accelerators, prototyping FeFET based accelerators, etc  (FERRO4EDGEAI project)
• Ultra-low power brain-inspired edge computing egines using memristor devices (NL-ECO project).
• Definition and  design of a micro-architecture of a neuromorphic system augmented with self-healing mechanism to deal with non-idealities (project SNS: Self-healing Neuromorphic Systems)

MSc projects 

At the moment, I do have many MSc projects, in different aspects of hardware dependability as well as development, design, implementation and prototyping of computation-in-memory based micro-architectures for edge AI applications. Obviously, we can always explore the potential of defining a new project with mutual interest. Examples of exiting MSc projects are:

• Hardware dependability
  • Fault modeling and test solutions for FeFET memories (in collaboration with industry partner).
  • Testing and design-for-test for memristor based computation-in-memory architectures for edge AI 
  • Built-in-Selft Test for Resistive Random Access Memories (RRAMs)
  • Built-in-Selft Test for Spin-Transfer Torque Magnetic Random Access Memories (STT-MRAMs)
  • Defect modeling and test solutions for periphery circuits in RRAMs
  • Defect modeling and test solutions for periphery circuits in STT-MRAMs
  • Replacing O(n2) memory test algorithms with O(n) or O(nlog(n)) algorithms for embedded memories (In collaboration with a semiconductor company)
  • Dealing with non-idealities (varability, degradation, ..) in memristor based computation-in-memory architectures for edge AI 
  • etc.
• Emeging computing paradigms based on emerging devices
  • Energy effecient brain-inspired micro-architectures using on-volatile devices
  • Marco simulation for new micro-architectures 
  • Dealing with non-idealies in memristor based computation-in-memory architetcures 
  • Periphery-array co-design for energy effecient and accurate computinng in computation-in-memory architectures 
  • implementation and prototyping of of different flavours of computation-in-memory accelrators for edge AI
  • etc.