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Sorin Cotofana

About

Currently, I am an Associate Professor with the Computer Engineering Laboratory, Electrical Engineering, Mathematics and Computer Science Faculty, Delft University of Technology, Delft, The Netherlands. I received the MSc degree in Computer Science from "Politehnica" University of Bucharest, Bucharest, Romania, and the PhD degree in Electrical Engineering from Delft University of Technology, The Netherlands.

I am an IEEE Fellow and a HiPEAC member.

My current research is focused on: (i) unconventional computation paradigms and computation with emerging nano-devices, (ii) the design and implementation of dependable/reliable systems out of unpredictable/unreliable components, and (iii) ageing assessment/prediction and lifetime reliability aware resource management.

I (co-)authored more than 250 papers in peer-reviewed international journals and conferences, received 12 Best Paper Awards in international conferences, e.g., 2016 IEEE/ACM International Symposium on Nanoscale Architectures, 2012 IEEE Conference on Nanotechnology, 2012 ACM/IEEE International Symposium on Nanoscale Architectures, 2005 IEEE Conference on Nanotechnology, and 2001 International Conference on Computer Design.

In the last decade, I have been involved in European Union funded research projects, e.g., i-RISC, 3DIM3, NEMSIC, as Principal Investigator and Work Package Leader.

I served as Associate Editor for IEEE Transactions on CAS I (2009-2011), IEEE Transactions on Nanotechnology (2008-2014), Microprocessors and Microsystems (2016-2017), and Nano Communication Networks (2010-2014);  Associate Editor in Chief for IEEE Transactions on Nanotechnology (2015 - 2019); Senior Editorial Board Member for IEEE Journal on Emerging and Selected Topics in Circuits and Systems (2016-2017); Steering Committee Member for IEEE Transactions on Multi-Scale Computing Systems (2014-2018); Chair of the Giga-Nano IEEE CASS Technical Committee (2013-2015); and IEEE Nanotechnology Council CASS representative (2013-2014).

I have been actively involved in the organization of numerous international conferences as General Chair (e.g., NANOARCH 2018), Technical Program Committee (TPC) Chair (e.g., NANOARCH 2012), Track Chair, (e.g., ISCAS 2014-2016), Special Sessions Chair, (e.g., ICECS 2016), Workshop Chair, (e.g., ESSCIRC 2013), and TPC Member (e.g., ISCAS, DATE, ARITH, NANOARCH, GLSVLSI).

Currently, I am Editor in Chief for IEEE Transactions on Nanotechnology, Associate Editor for IEEE Transactions on Computers, CASS BoG member (2020-2022), and CASS Distinguished Lecturer (2019-2020).

Presently, I am co-Principal Investigator of the EU FET Open “Spin Wave Computing for Ultimately-Scaled Hybrid Low-Power Electronics” (CHIRON) project and my teaching includes MSc Computer Engineering courses Modern Computer Architecture (ET4074), Computer Arithmetic (ET4170), and Processor Design (ET4171).

Publications