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Dblp

Anteneh Gebregiorgis

About

Anteneh Gebregiorgis is currently a Postdoctoral researched with the Quantum and Computer Engineering (QCE) department, Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Delft University of Technology (TU-Delft).

Dr. Gebregiorgis received his PhD degree in Computer Science from Karlsruhe Institute of Technology (KIT), Germany, in 2019 where his research was on reliable and low-power architecture design for energy-constrained devices. Currently, he is a postdoctoral researcher in the department of Quantum and Computer Engineering, Faculty of Electrical Engineering, Mathematics and Computer Science (EEMCS), Delft University of Technology (TU Delft), The Netherlands, where his research focuses on RRAM based CIM architecture for neuromorphic computing. From 2017 to 2018 he was a visiting scholar with the nano-electronics research laboratory, Purdue University, USA, where he was working on designing energy-efficient neuromorphic architectures.

His current research focuses on neuromorphic computing using emerging device technologies such as Resistive Random Access Memory (RRAM) with non-conventional architecture, computation-in-memory, targeting edge applications. His research also includes the test and reliability aspect of these emerging devices and architectures.

Research

My current research is streamlined into  two research lines. The first research line focuses on neuromorphic computing with emerging device technologies, while my second research line investigates the test and reliability aspect of emerging devices and architectures.

Neuromorphic computing with emerging devices:
The main focus of this research line is to develop energy-efficient neuromorphic hardware architecture for targeted energy-constrained platforms such as edge computing. This can be realized through non-conventional computing paradigm, Computation-in-Memory (CIM) using emerging non-volatile memory devices. The main activities in this direction include:
Circuit design:  Design of efficient bit-cell, periphery circuits such as ADC, DAC as well as crossbar array for CIM operation.
Architecture design: design and optimization of architectural blocks such as crossbar array, control logic and periphery circuits.

Test and reliability research line:
This research line focuses on investigating the reliability and testability aspect of emerging devices and architectures and develop techniques to enhance their dependability. Some of the test and reliability solutions include fault-tolerant design, efficient Design for Testability (DFT) techniques etc.

Publications

Students

PhD students I am working with:
•    Sumit Diware
•    Abhairaj Singh
•    Moritz Fieback
•    Guilherme Cardoso Medeiros

Ongoing MSc students:
•    Winay Sewnarain
•    David Vrijenhoek
•    Jan-Andres Galvan Hernandez
•    Alexandra Dobrita
•    Kevin Kevin Shidqi
•    Duco Veldhuijzen

Graduated MSc Students:
•    Shubhendu Shrivastava, Stress Aware Quiescent Current Test Optimization, in collaboration with NXP,  Aug 24, 2021
•    Artemis Zografou, RRAM-based fault-tolerant Binary Neural Networks, July 27, 2021
•    Zacharia Rudge, RRAM-based Low-Power Neuromorphic Computing Engine for Space Applications, December 22, 2021